This application claims the benefit of the Korean Application No. P2001-43140 filed on Jul. 18, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an image sensor, and more particularly, to a complementary metal oxide semiconductor (CMOS) image sensor in which a charge storage gate is formed at one side of a photodiode region to increase charge capacity for each cell, thereby improving characteristics of a device.
2. Discussion of the Related Art
Most of charge-coupled devices (CCDs) developed and used as an image pickup device are driven using a higher voltage of +15Vxcx9cxe2x88x929V than a voltage of CMOS circuits. Since the process of manufacturing a CCD is similar to the process of manufacturing a bipolar transistor, the process cost of a CCD is higher than that of a CMOS. To solve such a problem, there has been provided a CMOS image sensor that can integrate an image sensor and peripheral chips having various functions into one chip and enables low voltage operation, low power consumption, and cheaper process cost. Also, the CMOS image sensor has the advantage in that it can be used for the process of manufacturing a CMOS transistor that enables the ultra-fine process. However, in spite of such advantages, the CMOS image sensor has a problem in picture quality. A newly suggested CMOS image sensor of a photo gate structure still has a limitation in improving picture quality due to the difference in charge efficiency between wavelength bands.
In the above respects, research and development of a CMOS image sensor of a new pixel structure is required.
A related art CMOS image sensor will now be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram of a pixel of a related art CMOS image sensor, and FIG. 2 is a sectional view of a pixel of the related art CMOS image sensor.
The CMOS image sensor of FIG. 1 has a 4-TR structure. Referring to FIG. 1, the CMOS image sensor includes a reset transistor 1 having a gate to which a reset signal RX is applied, one electrode connected with a floating node 2, and the other electrode connected to a VDD terminal, a source-follower transistor 3 having a gate connected with the floating node 2 and one electrode connected with the VDD terminal, a select transistor 4 having a gate to which a row select signal is input and one electrode serially connected to the source-follower transistor 3 to connect to an output terminal Vout, a transfer transistor 5 having one electrode connected with the floating node 2 and a gate to which a transfer signal TX is input to transfer storage charge when reading the storage charge, and a photodiode 6 provided between the transfer transistor 5 and a ground terminal.
In addition to the aforementioned image sensor of a 4-TR structure, examples of a CMOS image sensor include a 3-TR structure and a 1-TR structure. The 3-TR structure has no transfer transistor and the 1-TR structure has only a select transistor.
The sectional structure of the related art CMOS image sensor will be described with reference to FIG. 2.
As shown in FIG. 2, a p type epitaxial layer 22 is formed on a p type semiconductor substrate 21.
An n type photodiode region 23 and a p type photodiode surface region 24 are formed within a surface of the p type epitaxial layer 22. Only the n type photodiode region 23 may be formed as the case may be.
An n+ type region 27 used as a floating diffusion region for sensing image charges is formed in the p type epitaxial layer 22 and spaced apart from the photodiode regions 23 and 24.
A transfer gate 25 is formed over the p type epitaxial layer 22 between the photodiode regions 23 and 24 and the n+ type region 27.
A reset gate 26 is formed on the p type epitaxial layer 22 at one side of the n+ type region 27.
The charge sensing operation of the aforementioned related art CMOS image sensor will be described with reference to FIGS. 3A to 3D.
FIGS. 3A to 3D illustrate the operation of generating and reading out charges of the related art CMOS image sensor.
As shown in FIG. 3A, signal charges are stored in a photodiode by an external incident light.
As shown in FIG. 3B, a read out node (floating node) is reset, and then, as shown in FIG. 3C, signal levels of the stored charges are transferred to the floating gate if a transfer signal VTX is input to a gate of a transfer transistor to turn on the transfer transistor.
In this state, as shown in FIG. 3D, the reset transistor is turned off and the potential of the floating node, which is a source terminal of the reset transistor, is varied by the stored signal charges. For this reason, the gate potential of the source-follower transistor is varied.
The variation of the gate potential of the source-follower transistor varies a bias of a source terminal of the source-follower transistor or drain node of the select transistor.
Once the low select signal VROW is input to the gate of the select transistor before the read out node (floating node) is reset, the select transistor outputs the potential difference between the reference potential of the reset read out node (floating node) and the signal charges generated in the photodiode to the output terminal.
The reset transistor is turned on by the reset signal after detecting signal levels by generating charges of the photodiode. Therefore, the signal charges are all reset.
The above operation is repeated so that the reference potential and the signal levels are read out.
However, the related art CMOS image sensor has several problems.
The charge capacity of the photodiode is determined by the area of the photodiode, the doping concentration of the n type photodiode, the impurity concentration of the substrate, and the doping concentration of the p type photodiode surface. The charge capacity of the photodiode is an important factor that influences characteristics of optical signals. The area of the photodiode is reduced as the pixel size is reduced to enhance resolution in the same chip area and to obtain price competition.
Under the circumstances, there is a limitation in obtaining the charge capacity by controlling the impurity density.
Accordingly, the present invention is directed to a CMOS image sensor that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a CMOS image sensor in which a charge storage gate is formed at one side of a photodiode region to increase charge capacity for each cell, thereby improving characteristics of a device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a CMOS image sensor includes a photodiode region generating image signal charges by converting image signals of light to electrical signals, and a charge storage gate formed near the photodiode region, wherein the charges of the photodiode region are partially or entirely transferred to a portion below the charge storage gate when the charges are generated, and the charges stored when the charges are read out are transferred to a read out node.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.